The present invention relates to a level shifter disposed between two logic circuits respectively driven by different power voltages for shifting the voltage level of an output signal of one of the logic circuits to supply the shifted voltage to the other logic circuit.
Recently, portable equipment to which power is supplied from batteries have been widely spread, and in order to elongate the driving time of the batteries, it is earnestly required to reduce the power consumption of a system used in such portable equipment. On the other hand, among these portable equipment, particularly cellular phones are required to have a large number of functions for, for example, e-mails, web browsing and games apart from its original communication function. Therefore, in a semiconductor integrated circuit included in such portable equipment, power voltages are changed in respective blocks therein in accordance with requested functions, so as to lower the power voltage in a block that is not required of a high speed operation. Thus, multifunctional performance and low power consumption are both attained. As a result, in some cases, power voltages are different in the respective internal blocks having different functions, and hence, it is necessary to provide a level shifter for shifting a signal level between these functional blocks.
A conventional general signal level shifter will now be described with reference to FIGS. 15 and 16. FIG. 15 is a diagram for showing the configuration of the level shifter and FIG. 16 is a diagram for showing its input waveform and output waveform.
In the level shifter shown in FIG. 15, when an input signal V(in) at an internal voltage level VDD1 is input, an output signal V(out) having been shifted in the level into an external voltage level VDD2 is output from an output terminal out as shown in FIG. 16. It is noted, in FIG. 16, that tpLH indicates a delay time from the rise of the input signal V(in) to the rise of the output signal V(out) and tpHL indicates a delay time from the fall of the input signal V(in) to the fall of the output signal V(out).
First, the change of the output signal V(out) caused when the input signal V(in) input from an input terminal in rises from 0 V to the internal voltage level VDD1 will be described. The internal voltage level VDD1 of the input signal V(in) is transferred to an inverter I1. The inverter I1 outputs a signal at L (0 V) level, and an inverter I2 outputs a signal at the internal voltage level VDD1. An input voltage to the gate of an NMOS transistor N1 becomes the internal voltage level VDD1, and therefore, the NMOS transistor N1 is turned on, and an input voltage to the gate of another NMOS transistor N2 becomes 0 V, and hence, the NMOS transistor N2 is turned off. As a result, an input voltage to the gate of a PMOS transistor P2 and an inverter I3 changes from the external voltage level VDD2 to 0 V, and hence, the output voltage of the inverter I3 is changed from 0 V to the external voltage level VDD2. At this point, since the PMOS transistor P2 is gradually turned on, the input voltage to the gate of a PMOS transistor P1 is changed from 0 V to the external voltage level VDD2, and hence the PMOS transistor P1 is turned off.
Next, the change of the output signal V(out) caused when the input signal V(in) input from the input terminal in falls from the internal voltage level VDD1 to 0 V will be described. In this case, the inverter I1 outputs a signal at the internal voltage level VDD1 and the inverter I2 outputs a voltage of 0 V. The input voltage to the gate of the NMOS transistor N1 becomes 0 V, and hence the NMOS transistor N1 is turned off, and the input voltage to the gate of the NMOS transistor N2 becomes the internal voltage level VDD1, and hence the NMOS transistor N2 is turned on. As a result, the input voltage to the gate of the PMOS transistor P1 is changed from the external voltage level VDD2 to 0 V. At this point, the PMOS transistor P1 is gradually turned on, and therefore, the input voltage to the gate of the PMOS transistor P2 and the inverter I3 is changed from 0 V to the external voltage level VDD2, and the PMOS transistor P2 is turned off. The output voltage of the inverter I3, namely, the output signal from the output terminal out, is changed from the external voltage level VDD2 to 0 V.
In the aforementioned operation, assuming that the voltage level of the input signal V(in), the power voltage levels VDD1 and VDD2 and the voltage level of the output signal V(out) are respectively set to predetermined fixed values, the design parameters such as the gate length and the gate width of each MOS transistor are optimized, so that the level shifter attains optimum rise and fall delay characteristics.
In the conventional level shifter, however, when the internal voltage level VDD1 and the external voltage level VDD2 are changed, a large time difference is caused between the rise delay time tpLH and the fall delay time tpHL of the output signal, and therefore, these delay times are disadvantageously ill balanced. The changes of the delay times caused in changing the power voltages are shown in FIG. 17. Specifically, FIG. 17 shows the characteristics of the rise delay time tpLH and the fall delay time tpHL of the output signal obtained when the internal power voltage level VDD1 and the external power voltage level VDD2 are changed. In this drawing, as the internal power voltage level VDD1 is changed to be higher, the rise delay time tpLH becomes shorter, and as the external power voltage level VDD2 is changed to be lower, the fall delay time tpHL becomes shorter and halfway (at approximately 1.35 V in this drawing) becomes longer. Accordingly, as the internal power voltage level VDD1 is set to be higher and the external power voltage level VDD2 is set to be lower, the balance between the delay times is more largely spoiled.
A technique to overcome this problem is described in, for example, Japanese Laid-Open Patent Publication No. 11-41090. In this publication, in order to make the rise and fall delay times well balanced, a control signal is externally generated to be input to a level shifter, so that the characteristics of the rise and fall delay times of the level shifter can be changed.
In this conventional level shifter, however, it is necessary to externally input a control signal to the level shifter, and therefore, the circuit scale of the whole semiconductor integrated circuit including the level shifter is increased. Accordingly, the number of wires is increased, resulting in disadvantageously complicating the whole circuit.